
Anandkumar Mahadevan Pillai
Current graduate student pursuing Masters in Electrical Engineering at University of Minnesota - Twin Cities with research interests... | San Jose, California, United States
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Anandkumar Mahadevan Pillai’s Location San Jose, California, United States
Anandkumar Mahadevan Pillai’s Expertise Current graduate student pursuing Masters in Electrical Engineering at University of Minnesota - Twin Cities with research interests in Digital/Mixed-Signal Design, FPGA-based design and Computer Architecture. Presently, seeking internships opportunities in these fields for summer 2016. Technical Skills: Expertise in: ►Digital logic design (RTL, gate and spice level), digital logic synthesis and test bench development ►ASIC design flow and custom layout design ►Analog and digital VLSI circuit design and experience in designing circuits like OP-AMP, current mirror, data converters ►Cache design, replacement strategies, dead block prediction strategies ►FPGA based hardware/software design and debug ►Programming languages like Verilog HDL, Verilog-A, C, C++ and good knowledge in Perl scripting language ►Embedded system design ►Xilinx core generators. Experience in using IP cores such as ZYNQ 7000 processor, clock wizard, AXI GPIO and block RAM ►EDA Tools such as: Cadence (Virtuoso, Spectre, Layout XL), HSPICE, Synopsys CosmoScope, Xilinx ISE (Core Generator, Plan Ahead and Chipscope), Xilinx Vivado, Mentor Graphics ModelSim, SimpleScalar ►Good understanding of device physics and sub-micron device fabrication flow
Anandkumar Mahadevan Pillai’s Current Industry Intel
Anandkumar
Mahadevan Pillai’s Prior Industry
Ieee
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Amrita Signal Processing And Integrated Circuits Research Labs Amrita Vishwa Vidyapeetham
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Amrita Vishwa Vidyapeetham
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Apple
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Intel
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Work Experience

Intel
Component Design Engineer
Thu Jun 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Apple
Physical Design Intern
Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Amrita Vishwa Vidyapeetham
Teaching Assistant
Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri May 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Amrita Signal Processing And Integrated Circuits Research Labs Amrita Vishwa Vidyapeetham
Research Associate
Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Ieee
Secretary, IEEE Industrial Electronics Student Chapter
Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Dec 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)